Inside a Hantek DSO-2090 USB Oscilloscope
2013/07/10 99 Comments
As part of my electronics test gears, I’ve recently got myself a cheap USB oscilloscope: a Hantek DSO-2090.
The DSO-2090 is marketed as an 100 MSPS with 60 MHz analog bandwidth, though the full sample rate is available only when using a single channel. As Hantek also sells similar models with higher performances, I immediately took the device apart to better understand how it works and to see if it can be pushed a bit more, especially regarding the realtime sample rate.
This post is a basic analysis of how this oscilloscope works with some consideration of its limits, and it may be interesting to better understand how a basic DSO works.
PCB and Block Diagram
The scope is realized with a standard 1.6mm 2 layer PCB, without using any fancy BGA or QFN components. This is basically a single shot dual channel DAQ, with an analog frontend, triggering circuit, ADC, some SRAM for fast temporary storage, a Cypress USB interface, and a CPLD to control the whole thing.
This is a picture of the PCB with the main elements highlighted (the shielding cover of channel 1 frontend has been removed):
The whole device operates from USB, so the PCB has a 3.3V fixed LDO (actually two in parallel… weird!) for digital devices and two DC/DC converters (U426 and U427) to get a stable dual +5V/-5V supply for the analog stuff.
The USB interface is implemented using a Cypress CY7C68013A, an 8051 based USB controller commonly used to interface FPGA and CPLD based DAQ to an host via USB. This kind of host interface is really common in these devices.
The Cypress also has a configuration EEPROM (U807) to allow device identification, but the actual firmware is loaded at runtime from the host.
Control CPLD and SRAM
The main component of the DSO is a Xilinx XC95288XL CPLD, in the 10ns speed variant and commercial temperature range. The CPLD is coupled with a pair of ISSI IS61LV256AL SRAM for realtime sample storage.
The CPLD is also attached to the ADC and other controllable components. The operating principle is quite simple in theory: the scope continuously records data from the ADC into the SRAM in a circular buffer, and stops for transferring the samples to the host when the trigger circuit shoots, keeping the acquisition delay into account. The CPLD is also used, basically as a port expander, to control other digital parts of the device, such as the analog switches.
It seems like the CPLD operates completely asynchronously from the USB bridge, and the whole thing can be easily overclocked by replacing the main 50MHz oscillator. I actually have my DSO-2090 running with a 125MHz (!) oscillator, and apart from some acquisition glitch at intermediate time/div settings it works just fine!
The two ADCs originally had their part number optimistically covered with a marker, but are actually a pair of TI ADC08060, which I replaced with two ADC08100. I did not see any improvement tough, so I think this mod is a waste of money, but at least confirms the part number.
The two ADCs are connected behind a HEF4052 (U50) analog multiplexer that is used to connect any ADC to any of the two channels. This is actually useful to operate the ADCs in interleaved mode on the same channel, and obtain a maximum sample rate of 2*CLK (100MSPS with the stock oscillator).
The analog multiplexer is controlled by the CPLD, and there seems to be a couple of clamping diodes (D1, the other is bottom mounted) into both signal paths from the frontend to the multiplexer. Also, a multi-turn trimpot is used to manually calibrate the ADC full scale voltage.
This little TSOP10 device (U20) seems to be a 4 channels SPI DAC, the actual part number is masked out. This is controlled by the Cypress USB interface and has two channels wired into a buffer (the signals are trough R130 and R131) and summed (in analog) to the two input signals to control the offset. One additional channel (see R128) is fed into the analog comparator of the triggering circuit.
The two input offset signals are buffered in a SOIC8 device (probably an OPAMP), mounted on the bottom side between the two input frontends.
The analog frontend is realised with discrete components, and it’s actually simpler than it seems.
The first two relays (RL1, RL2) are used to engage or bypass two /10 attenuators into the signal path, including a tuned compensation network (that’s what the trimmable caps on the bottom side are for).
The third relay is used to bypass a reasonably big capacitor in series with the signal, after the main attenuators. This is used to implement DC or AC signal coupling.
After the AC relay, the signal is fed into a SST5912 JFET MOSFET (U33), and then into a compensated resistor divider network used to implement the usual /1 /2 /5 attenuation sequence, with the actual tap points going into another 4052 analog multiplexer.
Finally, the signal is fed into what seems to be an OPAMP (U9) to be amplified and summed to the requested offset, ready to go into the ADC multiplexer.
Also, just after the 4052, a small signal MOSFET (Q2) allows to engage a small capacitor from signal to ground, to add some sort of limited bandwidth mode.
All relays are wired into a 74HC244 octal buffer and controlled by the Cypress interface, while the analog multiplexer is wired into the CPLD directly.
Somewhere into the signal path, a couple of SOT23 diodes (Q8 and Q9) on the bottom side of the PCB are used to clamp the signal into safety limits.
Triggering is handled by an analog comparator (U15), connected with another HEF4052 to either one of the two channels, or the external trigger.
The triggering circuit also features a 2×1 pin strip input for trigger out signal, and signal MOSFET (Q4) to engage an RC filter into the signal for noise rejection. Curiously enough, the resistor is actually shorted with a 0 Ohm, so the designer decided to use the actual internal circuitry of the 4052 as part of the filtering.
Hacking and Design Limitations
The whole design is quite easy to understand, and the most interesting thing to hack is the actual CPLD clocking to allow for a higher single shot sample rate.
The stock configuration is to use a 50MHz oscillator, allowing up to 100MSPS in single channel mode. Hantek also sells a 150MSPS model, which spots two oscillators: a 50MHz and a 75MHz one (there are two slots on the PCB).
I actually tried to replace the stock oscillator with different values (75, 100 and 125MHz), and while the 75MHz works fine, with the 100 and 125MHz ones, there are some acquisition glitches at intermediate time divisions – some samples are plain wrong. This only seems to happen on the first channel if both are enabled, and seems to get worse when touching one of the two SRAM data lines, so it may just be a limitation of the PCB layout or the CPLD itself.
Anyway, I’m currently running this thing with a 125MHz oscillator, and it seems to work fine with most timebases, so that’s 250MSPS for the price of an oscillator… worth a try!
As for the software, I’m using the device in Linux with a modified version of OpenHantek. For the sample rate, the application just requests a specific clock divisor based on the hardcoded input clock value, so it’s really easy to modify the source code to specify a different value for the CPLD oscillator frequency.
That’s it! This little device does not pretend to have the performances of a real DSO, but I think it’s well worth the price considering that you can just sneak it into your laptop bag and have a basic oscilloscope with you all the time.
The best part for me is that with the OpenHantek software, it works just fine in a Linux system, and has a nice full open source software for the control application. Support for SigRok is on the way too.
The bad part is that there are not many advanced features. If you are used to fancy high-end multi giga samples per seconds scopes with tons of signal analysis and complex trigger capabilities, just forget about this and start saving money for a real device. On the other side, if you just need a basic scope that works fine under Linux, go for it!